The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2005

Filed:

Jun. 09, 2003
Applicant:

Ju-young Lee, Gyeongsangbuk-do, KR;

Inventor:

Ju-Young Lee, Gyeongsangbuk-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F 1136 ;
U.S. Cl.
CPC ...
Abstract

The present invention is related to an array substrate for use in a liquid crystal display. The array substrate includes a transparent substrate; a plurality of gate lines arranged over the transparent substrate in a transverse direction; a plurality of data lines arranged over the transparent substrate in a longitudinal direction substantially perpendicular to the plurality of gate lines, intersections of the plurality of data lines and the plurality of gate lines defining a plurality of pixel regions; a gate driver contacting ends of the plurality of gate lines and sequentially scanning a gate pulse to the plurality of gate lines; a data driver contacting ends of the plurality of data lines and applying a data pulse to the plurality of data lines; a plurality of pixel electrodes disposed in the plurality of pixel regions; a plurality of first thin-film transistors disposed in the plurality of pixel regions, each first thin-film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode connected to the pixel region; a feed line outputting an OFF voltage to the plurality of first thin-film transistors; and a plurality of second thin-film transistors contacting each other and connecting the feed line to the plurality of gate lines.


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