The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2005
Filed:
Mar. 05, 2003
Makoto Ogawa, Okayama, JP;
Akira Urakami, Okayama, JP;
Kazuhiko Ohashi, Okayama, JP;
Japan Gore-Tex, Inc., Tokyo, JP;
Abstract
A dielectric film for a printed wiring board that has excellent heat resistance, moisture resistance, insulation properties, adhesiveness, ease of handling, ease of processing, and the like, and possesses low elasticity and high elongation as stress relief functions. The dielectric film has drawn porous polytetrafluoroethylene used as the base material; this is impregnated with an adhesive or fusible resin; the post-solidification tensile modulus of elasticity is 0.1 to 1.8 GPa; and the tensile elongation at break (at 25° C.) is at least 4.0%. A semiconductor device, comprising a multilayer printed board having a plurality of circuit layers, and a semiconductor element mounted on the multilayer printed board, this semiconductor device having an insulating/adhesive layer with a stress relief function between the outermost circuit layer of the multilayer board on the side of the semiconductor element, and the circuit layer adjacent thereto; and the insulating/adhesive layer is formed from the dielectric film. Also, a printed wiring board therefor.