The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2005
Filed:
Jun. 03, 2004
Peter Rabkin, Cupertino, CA (US);
Hsingya Arthur Wang, San Jose, CA (US);
Kai-cheng Chou, San Jose, CA (US);
Peter Rabkin, Cupertino, CA (US);
Hsingya Arthur Wang, San Jose, CA (US);
Kai-Cheng Chou, San Jose, CA (US);
Hynix Semiconductor, Inc., Kyoungki-do, KR;
Abstract
A gate electrode is formed over but is insulated from a semiconductor body region for each of first and second transistors. Off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a DDD implant is performed to form DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, main spacers are formed adjacent the off-set spacers of at least the first transistor. A LDD implant is performed to form LDD source and LDD drain regions for the second transistor. After forming the main spacers, a source/drain (S/D) implant is carried out to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions.