The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2005
Filed:
Oct. 31, 2002
Alireza S. Kaviani, San Jose, CA (US);
Patrick T. Lynch, Edenderry, IE;
Paul G. Hyland, Naas, IE;
Patrick J. Crotty, San Jose, CA (US);
Tao Pi, Sunnyvale, CA (US);
Alireza S. Kaviani, San Jose, CA (US);
Patrick T. Lynch, Edenderry, IE;
Paul G. Hyland, Naas, IE;
Patrick J. Crotty, San Jose, CA (US);
Tao Pi, Sunnyvale, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for reducing power dissipation and jitter in a delay line is described. The delay line includes a plurality of delay elements. At least one of the plurality of delay elements includes a gate terminal configured to receive gate control signals for activating or deactivating one or more of the delay elements. The delay line further includes gate control circuitry for providing gate control signals to the gate terminal of at least one of the plurality of delay elements.