The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2005

Filed:

Dec. 19, 2002
Applicants:

Hirofumi Komori, Yokohama, JP;

Mitsuru Yoshikawa, Tsuchiura, JP;

Inventors:

Hirofumi Komori, Yokohama, JP;

Mitsuru Yoshikawa, Tsuchiura, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2701 ;
U.S. Cl.
CPC ...
Abstract

The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating filmsandand outer side wall insulating filmsandformed at both sides of the gate electrodesandin both high breakdown voltage transistor TRand transistor TRfor low voltage drive, and heavily doped regionis formed in breakdown voltage transistor TRusing both inner side wall insulating filmand outer side wall insulating filmas masks so that offset dis controlled by the combined widths of the two side wall insulating films. In transistor TRfor low voltage drive, heavily doped regionis formed using only inner side wall insulating filmas the mask, and offset dis controlled.


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