The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2005

Filed:

Jul. 27, 2001
Applicants:

Carol L. Thompson, San Jose, CA (US);

Michael L. Zi Gler, Campbell, CA (US);

Jerome C. Huck, Palo Alto, CA (US);

Lawrence D. K. B. Dwyer, South San Francisco, CA (US);

Inventors:

Carol L. Thompson, San Jose, CA (US);

Michael L. Zi gler, Campbell, CA (US);

Jerome C. Huck, Palo Alto, CA (US);

Lawrence D. K. B. Dwyer, South San Francisco, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 945 ;
U.S. Cl.
CPC ...
Abstract

A method for reducing cache memory misses in a computer that performs context switches between at least a first context and a second context. A First logic identifies a first prefetch region in a first memory element and a second logic identifies critical memory references within the first prefetch region during compilation of a computer program. The critical memory references within the first prefetch region correspond to data in cache memory if a context switch occurs from a process or thread associated with the second context to a process or thread associated with the first context during program execution. Third logic prefetches data associated with the identified critical memory references and stores the prefetched data in cache memory prior to a process or thread associated with the first context being resumed when a switch from the second context to the first context occurs during program execution.


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