The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2005
Filed:
May. 10, 2001
Iwen Yao, San Diego, CA (US);
Da-shan Shiu, San Jose, CA (US);
Iwen Yao, San Diego, CA (US);
Da-Shan Shiu, San Jose, CA (US);
Qualcomm Incorporated, San Diego, CA (US);
Abstract
Techniques to efficiently generate memory addresses for a Turbo code interleaver using a number of look-up tables. An interleaver includes a storage unit, sets of tables, and an address generator. The storage unit stores K elements for a data packet at locations representative of an R×C array, with the elements being stored in a first (e.g., linear) order and provided in a second (e.g., interleaved) order. A first set of table(s) stores sequences (e.g., inter-row permutation sequences P, P, P, and P) used to perform row permutation of the array to map from the first order to the second order. A second set of table(s) stores sequences (e.g., intra-row base sequences and prime number sequences) used to perform column permutation. The address generator receives a first address for the first order and generates a corresponding second address for the second order based on sequences stored in the tables.