Synchronized signal transfer system

Abstract

A memory system for a data processor whereby a plurality of memory devices, or storage chips, are coupled to a memory controller. There may be one, two, or more such memory devices, wherein some of the memory devices may be coupled to the memory controller via a single data bus, with an alternative embodiment including a second plurality of such memory devices coupled to the memory controller via a second data bus. Two separate clock buses are used to transport data between the memory controller and the various memory devices. A first clock bus is used to synchronize the transfer of data from the memory controller to a memory device. This clock bus will have a clock signal generated at the memory controller through a clock generation circuitry as a function of a system clock received by the memory controller. A similar clock generation circuitry at the memory device will receive the clock signal in order to synchronize the transfer of the data from a sending latch of the memory controller to a receiving latch in the memory device. A separate clock bus is used to transfer data from a memory device to the memory controller. Again, a clock signal is generated at the memory controller and sent on the second clock bus to the memory device. Clock generation circuits at the memory controller and at the memory device synchronize the sending latch at the memory device with the receiving latch at the memory controller. Both of the clock signals are synchronized with each other and with the received system clock.