The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2005
Filed:
Jun. 18, 2003
Charles F. Shelor, Arlington, TX (US);
Charles F. Shelor, Arlington, TX (US);
VIA-Cyrix, Inc., Fremont, CA (US);
Abstract
A power saving hierarchical clock gating circuit includes a first level clock gate, a plurality of second level clock gates connected to the first level clock gate, and a plurality of third level clock gates for selectively providing a clock signal to a functional block. Each third level clock gate is connected between a second level clock gate and a register, or other low level device, of the functional block for selectively providing the clock signal to the register. Accordingly, the clock signal is conveyed from the first level clock gate through a second level and a third level clock gate to a register when the corresponding first, second, and third level clock gates are activated by associated decision logic.