Vcdl with linear delay characteristics and differential duty-cycle correction

Abstract

A voltage-controlled delay line (VCDL) comprises a series of delay cells outputting a clock output signal having a delay relative to a clock input signal input to the series of delay cells. A duty-cycle correction section corrects the duty cycle of the clock output signal by providing opposite current outputs which are fed back to the series of delay cells to substantially simultaneously charge and discharge current of the series of delay cells in opposite directions. A control current input to the series of delay cells controls the amount of the delay. A voltage-to-current converter converts a control voltage into the control current so that the delay changes substantially linearly as the control voltage changes. The method for using the VCDL to produce linear delay is also included. The VCDL can be used in a delay-locked loop (DLL).