Digital data storage subsystem including arrangement for increasing cache memory addressability

Abstract

A memory manager for use in connection with a memory comprises a memory access request receiver module, an address translation module and a memory access operation control module. The memory access request receiver module is configured to receive an access request requesting an access operation in connection with the memory, the access request including an address. The address translation module is configured to, (i) if the access request requests an access operation in connection with one of a plurality of sections of the memory, provide the address in the access request as an absolute address identifying at least one storage location in the one section; and (ii) if the access request requests an access operation in connection with another of said sections, generate an absolute address from the address provided in the access request, the address in the access request including a segment identifier and an offset, the address translation module being configured to process the segment identifier and offset to generate an absolute address identifying at least one storage location in the other of said sections. The memory access operation control module is configured to perform an access operation in connection with the memory using the absolute address generated by the address translation module.