The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2005
Filed:
Jan. 17, 2003
Frederick A. Perner, Palo Alto, CA (US);
James R. Eaton, Jr., Palo Alto, CA (US);
Kenneth K. Smith, Boise, ID (US);
Ken Eldredge, Boise, ID (US);
Lung Tran, Saratoga, CA (US);
Frederick A. Perner, Palo Alto, CA (US);
James R. Eaton, Jr., Palo Alto, CA (US);
Kenneth K. Smith, Boise, ID (US);
Ken Eldredge, Boise, ID (US);
Lung Tran, Saratoga, CA (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.