The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2005

Filed:

Dec. 14, 2001
Applicants:

Rohit Garg, Seattle, WA (US);

Chris Yoochang Chung, Lynnwood, WA (US);

Coskun Mermer, Mountlake Terrace, WA (US);

Donglok Kim, Seattle, WA (US);

Yongmin Kim, Seattle, WA (US);

Inventors:

Rohit Garg, Seattle, WA (US);

Chris Yoochang Chung, Lynnwood, WA (US);

Coskun Mermer, Mountlake Terrace, WA (US);

Donglok Kim, Seattle, WA (US);

Yongmin Kim, Seattle, WA (US);

Assignee:

University of Washington, Seattle, WA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 1120 ;
U.S. Cl.
CPC ...
Abstract

A boundary macroblock of a video object is padded without significant synchronization overhead between a host processor and an existing coprocessor. The host processor determines horizontal and vertical graphics primitives as a function of shape data stored in a host memory. The shape data determine whether a dot, a line, or a rectangle primitive should be used to pad transparent pixels in the macroblock. The host processor communicates the primitives to a coprocessor, which renders the primitives in an interleaved pipeline fashion to pad transparent pixels of the macroblock based on texture data stored in video memory. The flow of primitives is in one direction from the host processor to the graphics coprocessor, and the texture data is not transferred back and forth between the host processor and coprocessor. This technique is especially useful for enabling acceleration of MPEG-4 video decoding utilizing existing coprocessors capable of accelerating MPEG-1/2 video decoding.


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