The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2005
Filed:
Nov. 28, 2003
Applicants:
Nitin Agarwal, Bangalore, IN;
Shakti Shankar Rath, Bangalore, IN;
Inventors:
Nitin Agarwal, Bangalore, IN;
Shakti Shankar Rath, Bangalore, IN;
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H03M 112 ;
U.S. Cl.
CPC ...
Abstract
A low-jitter clock distribution circuit, used in an integrated circuit having multiple analog-to-digital converters (ADCs), includes a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor. The ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter is equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by the semiconductor fabrication process.