The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2005

Filed:

Jun. 20, 2003
Applicants:

Guido Retz, Ardmore, IE;

David Philip Burton, Limerick, IE;

Inventors:

Guido Retz, Ardmore, IE;

David Philip Burton, Limerick, IE;

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03G 516 ; H03G 310 ; H03F 304 ;
U.S. Cl.
CPC ...
Abstract

A differential variable gain amplifier () comprises eight identical variable gain stages (to) which are arranged in two groups, namely, a high gain group () and a low gain group (). The first gain stage () is coupled directly to a pair of positive and negative main input terminals () for receiving a differential input signal to be amplified. A pair of voltage divider impedance chains () comprising identical capacitors (Cto C) define taps (to) through which the input signal is applied to the corresponding gain stages (to) in progressive steps of attenuation. Each gain stage () comprises a pair of identical variable gain amplifier elements () which amplify the respective positive and negative ends of the differential input signal. Only one of the gain stages (to) is selected at any one time by a control circuit. The outputs from the gain stages () of the high gain group () are applied to positive and negative high gain output terminals (). The output of the gain stages () of the low gain group () are applied on positive and negative low gain output terminals (). A pair of selectively activatable shunt-shunt feedback circuits () each comprising a variable gain feedback amplifier () provide variable shunt impedance at the main input terminals () for maintaining the input impedance of the variable gain amplifier () within a predetermined input impedance range as the gain of the variable gain amplifier () is varied, and when the variable gain amplifier () is operating at the high end of its gain range. A passive shunt impedance circuit () comprising a plurality of resistive shunt impedance elements are independently selectively shuntable across the main input terminals () for maintaining the input impedance of the variable gain amplifier () within the predetermined input impedance range when the variable gain amplifier () is operating at the low gain end of its gain range.


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