The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2005

Filed:

Dec. 13, 2002
Applicants:

Wanli Chang, Saratoga, CA (US);

Andy Lee, San Jose, CA (US);

Cameron Mcclintock, Mountain View, CA (US);

Richard Cliff, Los Altos, CA (US);

Richard Yen-hsiang Chang, San Jose, CA (US);

Inventors:

Wanli Chang, Saratoga, CA (US);

Andy Lee, San Jose, CA (US);

Cameron McClintock, Mountain View, CA (US);

Richard Cliff, Los Altos, CA (US);

Richard Yen-Hsiang Chang, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19177 ;
U.S. Cl.
CPC ...
Abstract

At least some of the interconnection signaling on a programmable logic device ('PLD') is by differential signaling using differential driver circuitry to apply differential signals to a pair of conductors that extend to differential receiver circuitry. Such differential interconnection signaling helps the PLD operate satisfactorily with lower power supply voltages. The conductors in each differential signaling pair may cross over one another at various intervals in order to help reduce the adverse effects of capacitive coupling between adjacent and parallel signaling paths.


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