The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2005

Filed:

Oct. 02, 2003
Applicant:

Geon-ook Park, Seoul, KR;

Inventor:

Geon-Ook Park, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 214763 ;
U.S. Cl.
CPC ...
Abstract

A fabrication method of a semiconductor device includes forming an interlayer dielectric film over an entire surface of a semiconductor substrate that includes a lower line. A barrier layer having an etching rate that is lower than an etching rate of the interlayer dielectric film is formed on the interlayer dielectric film. The barrier layer is selectively etched to expose a predetermined region of the interlayer dielectric film. Next, a photoresist pattern is formed on the barrier layer having an opening of a predetermined area corresponding to the exposed region of the interlayer dielectric film. The opening of the photoresist pattern has an area that is greater than an area of the exposed region of the interlayer dielectric film. The line opening and the via are then simultaneously formed by etching the exposed regions of the barrier layer and the interlayer dielectric film. Finally, a metal plug is formed by filling the line opening and the via with a metal material.


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