The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2005

Filed:

May. 19, 2003
Applicants:

Francis Gabriel Celii, Dallas, TX (US);

K. R. Udayakumar, Dallas, TX (US);

Scott R. Summerfelt, Garland, TX (US);

Theodore S. Moise, Dallas, TX (US);

Inventors:

Francis Gabriel Celii, Dallas, TX (US);

K. R. Udayakumar, Dallas, TX (US);

Scott R. Summerfelt, Garland, TX (US);

Theodore S. Moise, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2100 ; H01L 218242 ;
U.S. Cl.
CPC ...
Abstract

A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.


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