The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
Jan. 18, 2001
Prakash Narain, San Carlos, CA (US);
Rajeev K. Ranjan, Santa Clara, CA (US);
Christopher Morrison, Sunnyvale, CA (US);
John M. Beardslee, Menlo Park, CA (US);
Rajiv Kumar, Santa Clara, CA (US);
Prakash Narain, San Carlos, CA (US);
Rajeev K. Ranjan, Santa Clara, CA (US);
Christopher Morrison, Sunnyvale, CA (US);
John M. Beardslee, Menlo Park, CA (US);
Rajiv Kumar, Santa Clara, CA (US);
Real Intent, Inc., Santa Clara, CA (US);
Abstract
A method and apparatus are described that facilitate validation of a hardware design having multiple hierarchical levels. In one embodiment, a representation of the hardware design is received, and the hardware design is validated by performing validation processing on a plurality of sub-problems. Each of the plurality of sub-problems covers a computationally feasible size of the hardware design at a corresponding hierarchical level. In another embodiment, validation of a hardware design includes making use of validation processing previously performed with respect to one or more modules included in the hardware design based on the hierarchical relationship between these modules and other modules included in the hardware design.