The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
May. 31, 2000
Kenneth W. Fernald, Austin, TX (US);
Danny J. Allred, Austin, TX (US);
Donald E. Alfano, Round Rock, TX (US);
Kenneth W. Fernald, Austin, TX (US);
Danny J. Allred, Austin, TX (US);
Donald E. Alfano, Round Rock, TX (US);
Silicon Labs CP, Inc., Austin, TX (US);
Abstract
A matrix of routing cells forming a cross-bar decoder (). Signal triplets () coupled to the cross-bar decoder () are assigned a priority. A register () provide outputs to the cross-bar decoder () to either activate or deactivate routing of the triplet signals () through the cross-bar decoder (). The routing cells () are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells () and are extracted at the column routing cells (). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder () until all high priority I/O pins are used. The outputs of the cross-bar decoder () are coupled to respective I/O pins () by way of respective driver circuits ().