The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6839654 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 04, 2005

Filed:

Feb. 07, 2003
Applicants:

René Röllig, Frankenberg, DE;

Jens Meyer, Dresden, DE;

Frank Barth, Radebeul, DE;

Alexander Krebs, Dresden, DE;

Inventors:

René Röllig, Frankenberg, DE;

Jens Meyer, Dresden, DE;

Frank Barth, Radebeul, DE;

Alexander Krebs, Dresden, DE;

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G04F 1000 ;
U.S. Cl.
CPC ...
Abstract

An on-chip event timer apparatus including a hardware timer and a debug interface. The hardware timer includes at least an up-counter for counting clocks of a clock signal, a match register for storing a programmable count value, and a comparator for monitoring whether the up-counter's count value matches the count value of the match register. The debug interface includes enable control unit for enabling the up-counter's operation based on a pre-defined relationship between a state of an enabled signal supplied to said up-counter and an internal state of the hardware timer. Additionally, the debug interface may comprise a clock divider connected to the enable control unit to reduce the clock's frequency in accordance with a pre-programmed divider value. Based on the received clock with the reduced clock frequency, the enable control unit adapts the up-counter's processing speed to the reduced clock frequency.


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