Systems for providing zero latency, non-modulo looping and branching of test pattern data for automatic test equipment

Abstract

An SRAM efficient ATE system that performs high speed nested loops without constraints on loop size or modularity and that loops and/or branches from any vector in a multiple vector accessed word to any vector in another multiple vector accessed word without incurring any time displacement. In one embodiment, the maximum required vector rate is less than or equal the average sustained data rate of the SDRAM and is less than or equal to the maximum access rate of the dual port SRAM's memory B. The output of the SDRAM's memory A consists of one control word and one vector (nV=1). The I/O port widths of the SRAM's memory B are the same. In another embodiment, the maximum required vector rate is greater than the average sustained data rate of the SDRAM's memory A, but is equal to or less than the maximum access rate of the SRAM's memory B. The output of the SDRAM's memory A consists of multiple control words and vectors. The input port of the SRAM's memory B is some multiple of the output port width. In another embodiment, the maximum required vector rate is greater than both the average sustained data rate of the SDRAM's memory A and the maximum access rate of the SRAM's memory B. The output of the SDRAM's memory A consists of one or more control words (nW) and nW×nV number of vectors. The input port of the SRAM's memory B is nW times the width of the output port. The output port of Memory B contains 2 or more vectors per word.