The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
Jul. 18, 2001
Wolfgang Ernst, München, DE;
Gunnar Krause, München, DE;
Justus Kuhn, München, DE;
Jens Lüpke, München, DE;
Jochen Müller, München, DE;
Peter Pöchmüller, München, DE;
Michael Schittenhelm, Poing, DE;
Wolfgang Ernst, München, DE;
Gunnar Krause, München, DE;
Justus Kuhn, München, DE;
Jens Lüpke, München, DE;
Jochen Müller, München, DE;
Peter Pöchmüller, München, DE;
Michael Schittenhelm, Poing, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.