The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
Apr. 25, 2003
Bradley J. Garni, Austin, TX (US);
Perry H. Pelley, Iii, Austin, TX (US);
Bradley J. Garni, Austin, TX (US);
Perry H. Pelley, III, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit () includes electrical circuitry () formed on a substrate (). An interconnect layer () is formed over the electrical circuitry (). In one example, a plurality of magneto-resistive random access memory cells (MRAM) () is implemented above the interconnect layer. Each of the MRAM cells comprises a magneto-resistive tunnel junction (MTJ) storage element. A transistor () is formed-over the interconnect layer (). In one embodiment, the transistor is implemented as a thin film transistor (TFT). In one embodiment the transistor is a select transistor and may be coupled to one or more of the MTJ storage elements. Access circuitry () is formed on the substrate () under the plurality of MRAM cells ().