The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6838643 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 04, 2005

Filed:

Jul. 18, 2002
Applicants:

Shouzou Kobayashi, Tokyo, JP;

Takamitsu Furukawa, Tokyo, JP;

Keisuke Tanaka, Tokyo, JP;

Kouhei Shimoyama, Tokyo, JP;

Akira Watanabe, Tokyo, JP;

Tadashi Nishimuro, Tokyo, JP;

Koki Muto, Tokyo, JP;

Azusa Yanagisawa, Tokyo, JP;

Katsuo Oshima, Tokyo, JP;

Inventors:

Shouzou Kobayashi, Tokyo, JP;

Takamitsu Furukawa, Tokyo, JP;

Keisuke Tanaka, Tokyo, JP;

Kouhei Shimoyama, Tokyo, JP;

Akira Watanabe, Tokyo, JP;

Tadashi Nishimuro, Tokyo, JP;

Koki Muto, Tokyo, JP;

Azusa Yanagisawa, Tokyo, JP;

Katsuo Oshima, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
F27B 514 ;
U.S. Cl.
CPC ...
Abstract

An apparatus for baking a semiconductor wafer having a resist pattern thereon includes a baking oven in which the semiconductor wafer is placed and heated, and a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer. The apparatus also includes a gas supply unit having a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven. A gas temperature controller controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.


Find Patent Forward Citations

Kobayashi, Shouzou. (2005). Method and apparatus for performing baking treatment to semiconductor wafer (U.S. Patent No. 6838643). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6838643

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