The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2004
Filed:
Jun. 14, 2002
Wilhelm E. Haller, Remshalden, DE;
Harald Mielich, Stuttgart, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to central processing units in computer systems, and in particular, it relates to a method and a respective hardware implementation of an add operation and a subtract operation. A combined add and subtract/compare logic is disclosed comprising: adding a less significant part of two add operands for generating a carry-out bit using a first carry network, adding a respective more significant part of the add operands for bit wise generating sum bits and carry bits, performing a combined subtract operation by bit wise operating a second carry network with respective bits of the more significant part of the subtract operand, and with respective ones of said sum bits, and said carry-out bit of said less significant part add operation, and the carry-out bits of said more significant part add operation. Speed is increased and chip area is saved.