The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2004
Filed:
Oct. 31, 2002
Ramkumar Subramanian, Sunnyvale, CA (US);
Jane V. Oglesby, Mountain View, CA (US);
Minh Van Ngo, Fremont, CA (US);
Mark S. Chang, Los Altos, CA (US);
Sergey D. Lopatin, Santa Clara, CA (US);
Angela T. Hui, Fremont, CA (US);
Christopher F. Lyons, Fremont, CA (US);
Patrick K. Cheung, Sunnyvale, CA (US);
Ashok M. Khathuria, San Jose, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.