The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2004
Filed:
Aug. 12, 2003
Applicant:
Inventor:
Koichi Morikawa, Tokyo, JP;
Assignee:
Oki Electric Industry Co., Ltd., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/01 ;
U.S. Cl.
CPC ...
H03K 3/01 ;
Abstract
A semiconductor integrated circuit operating in an active state and a sleep state has a power line that is branched through a first transistor to a first virtual power line and through a second transistor to a second virtual power line. The first transistor is switched on in the active state and off in the sleep state; the second transistor is switched off in the active state and on in the sleep state. The first virtual power line powers logic circuits. The second power line powers a memory circuit that stores necessary logic-circuit signal levels during the sleep state. The memory circuit does not consume power in the active state.