Method and arrangement for frequency doubling

Abstract

To generate an output signal ( ) the frequency of which is twice the frequency of an input signal ( ), a delayed signal ( ) which is delayed relative to the input signal ( ) by a quarter of the latter's cycle period is generated and the output signal ( ) is then generated as the difference between the rectified input signal ( ) and the rectified delayed signal ( ). The input signal ( ) and the delayed signal ( ) are advantageously rectified by using differential signals each comprising a positive component signal ( ) and a negative component signal ( ). A respective one of two transistors connected in parallel is driven by a positive component signal ( ) and a negative component signal ( ) in such a way that a positive half-wave causes the relevant transistor ( ) to conduct and the relevant transistor ( ) blocks in a negative half-wave. The rectified input signal ( ) or delayed signal ( ) is obtained from the two component currents flowing through the pairs of transistors ( ) connected in parallel when the currents are added. The rectified input signal ( ) and delayed signal ( ), which are in the form of current signals, can be passed through two resistors ( ) to enable corresponding voltage signals to be generated across the latter and the output signal ( ) to be picked off from the two resistors ( ).