The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2004
Filed:
Jul. 19, 2002
Chang-sik Yoo, Suwon, KR;
Kye-hyun Kyung, Suwon, KR;
Samsung Electronics Co., Ltd., Kyungki-do, KR;
Abstract
An integrated circuit memory device for use in a memory system receives predetermined command/address signals from a memory controller and reads and writes data in response to the command/address signals. The memory device includes at least one input/output terminal that inputs/outputs data from/to the memory controller via a data input/output bus, at least one termination resistor, and an active termination control signal generator that generates a control signal to control active termination of the at least one data input/output terminal in response to a chip selection signal from the memory controller. The memory device also includes at least one switch coupled in series with the at least one termination resistor between the at least one input/output terminal and a predetermined voltage wherein the at least one switch is switched on/off in response to the control signal such that the at least one input/output terminal is connected/disconnected to/from the predetermined voltage responsive to the control signal and such that the at least one termination resistor is coupled in series between the predetermined voltage and the at least one input/output terminal when the at least one switch is switched on and such that the at least one input/output terminal is decoupled from the predetermined voltage when the at least one switch is switched off. Related memory systems and methods are also discussed.