The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2004
Filed:
Feb. 27, 2003
Andrey V. Zagrebelny, Eagan, MN (US);
Daniel J. Arnzen, Eden Praire, MN (US);
Yitzhak Gilboa, San Jose, CA (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A dummy structure pattern for fabricating a substantially planar surface within an inactive region of a semiconductor topography is provided. In particular, a semiconductor topography is provided which includes an inactive region comprising a sacrificial annular dummy structure configured to surround an area larger than a square of a minimum critical dimension of a device arranged within an active region of the semiconductor topography. In a preferred embodiment, the area is exclusively designated for a formation of an isolation structure within the semiconductor substrate of the semiconductor topography. As such, a semiconductor topography is provided which includes a separate isolation structure arranged within a spacing of a contiguous isolation structure, which is arranged in a grid pattern within a portion of a semiconductor substrate. Moreover, a semiconductor device is provided which includes an inactive region with a plurality of similarly sized and uniformly arranged annular diffusion regions.