Geometry-controllable design blocks of mos transistors for improved esd protection

Abstract

An MOS transistor in the surface of a semiconductor substrate ( ) of a first conductivity type, which has a grid of isolations ( ) in the surface, each grid unit surrounding a rectangular semiconductor island ( ). Each island contains three parallel regions of the opposite conductivity type: the center region ( ) is operable as the transistor drain and the two other regions ( and ), abutting the isolations, are operable as transistor sources. Transistor gates ( and ) are between the parallel regions, completing the formation of two transistors having one common drain. Electrical contacts ( ) are placed on both source regions and the drain region. The source contacts are placed so that the spacing ( ) between each contact and its respective isolation is at least twice as large as the spacing ( ) between each contact and the gate. A plurality of these islands are interconnected to form a multi-finger MOS transistor having increased ESD failure threshold current by spreading the power dissipation and thus reducing the current localization without impacting the drain-to-substrate capacitance.