The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 2004
Filed:
Nov. 27, 2001
Yoshiyuki Uchinono, Hirakata, JP;
Kazuo Sawada, Katano, JP;
Yasufumi Masaki, Hirakata, JP;
Masahide Muto, Kobe, JP;
Matsushita Electric Works, Ltd., Osaka, JP;
Abstract
A molded interconnect device (MID) having a multilayer circuit of a reduced thickness, in which a layer-to-layer connection(s) is formed with high reliability, is provided as a multilayer circuit board. The multilayer circuit board comprises a substrate having a first surface and a second surface extending from an end of the first surface at a required angle relative to the first surface, and the multilayer circuit formed on the first surface and composed of a plurality of circuit layers. Each of the circuit layers is provided with a conductive layer having a required circuit pattern and an insulation layer formed on the conductive layer by film formation. The layer-to-layer connection of the multilayer circuit is made through a second conductive layer formed on the second surface of the substrate.