The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2004

Filed:

Oct. 09, 2001
Applicant:
Inventors:

John C. Carson, Corona Del Mar, CA (US);

Volkan H. Ozguz, Aliso Viejo, CA (US);

Assignee:

Irvine Sensors Corporation, Costa Mesa, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 1/228 ; H04L 1/256 ; H01L 2/900 ; H01L 2/3387 ; H01L 3/900 ;
U.S. Cl.
CPC ...
H04L 1/228 ; H04L 1/256 ; H01L 2/900 ; H01L 2/3387 ; H01L 3/900 ;
Abstract

A compact multi-stage switching network ( ), and a router ( ) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports ( ) to selected ones of a second plurality of output ports ( ) comprising: a first stack ( ) of IC switching layers ( ) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit ( ); a second stack ( ) of IC switching layers ( ) that are stacked in physical contact with one another, each IC switching layer ( ) containing at least one switching element circuit ( ); and interconnecting circuitry ( ) that connects the first stack ( ) of IC layers to the second stack ( ) of IC layers to form the compact multi-stage switching network. The stacks ( ) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection. Also contemplated are the use of superconducting IC switching circuits ( ) and a suitable superconducting cooling housing ( ), as permitted by the compact nature of the multi-stage switching network ( ), in order to operate at high speed and low power.


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