The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 2004
Filed:
Oct. 30, 2002
Frank K. Baker, Jr., Austin, TX (US);
Alexander Hoefler, Austin, TX (US);
Erwin J. Prinz, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor nonvolatile memory cell ( ) comprising a split-gate FET device having a charge-storage transistor ( ) in series with a select transistor ( ). A multilayered charge-storage gate dielectric ( ) extends over at least a portion of the source ( ) and a first portion ( ) of the channel of the FET. A select gate dielectric ( ), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain ( ) and a second portion ( ) of the channel. A monolithic gate conductor ( ) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer ( ). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.