The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 2004

Filed:

May. 16, 2003
Applicant:
Inventors:

Hyun Park, Victor, NY (US);

Daniel E. McCauley, Watkins Glenn, NY (US);

Mike S. H. Chu, Lewiston, NY (US);

Assignee:

Ferro Corporation, Cleveland, OH (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C04B 3/5468 ;
U.S. Cl.
CPC ...
C04B 3/5468 ;
Abstract

Multilayer ceramic chip capacitors which satisfy X7R requirements and which are compatible with reducing-atmosphere sintering conditions so that non-noble metals such as nickel, copper, and alloys thereof may be used for internal and external electrodes are made in accordance with the invention. The capacitors exhibit desirable dielectric properties (high capacitance, low dissipation factor, high insulation resistance), excellent performance on highly accelerated life testing, and very good resistance to dielectric breakdown. The dielectric layers preferably contain BaTiO as the major component and Mn O Y O , Ho O , CaCO , SiO , B O , Al O , MgO, and CaO as minor constituents. They are batched in a proportion that there are preferably present 99.00 to 98.5 wt. % BaTiO , 0.336 to 0.505 wt. % Mn O , 0.198 to 0.296 wt. % Y O , 0.132 to 0.198 wt. % Ho O , 0.199 to 0.299 wt. % CaCO , 0.057 to 0.085 wt. % SiO , 0.039 to 0.058 wt. % B O , 0.018 to 0.027 wt. % Al O , 0.016 to 0.025 wt. % MgO and 0.005 to 0.007 wt. % CaO. The B O , SiO , MgO, Al O , and CaO are preferably present in the form of pre-reacted glass. The preferred form of the invention may be sintered in the temperature range 1,200 to 1,300° C. in a reducing atmosphere. Additionally, a re-oxidation procedure may be utilized during the sintering cycle to optimize the resistance of the ceramic to dielectric breakdown.


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