The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2004
Filed:
Dec. 19, 2001
Mark H. Groo, Scotts Valley, CA (US);
Seagate Technologies LLC, Scotts Valley, CA (US);
Abstract
Apparatus and method for generating a divided clock signal. A ring counter is provided with a sequence of output states. During steady-state operation, a different one of the output states is set at a first logical level and each of the remaining output states is set at a second logical level at each successive clock transition in a master clock signal. A gate network uses the respective logical levels of the output states to generate the divided clock signal. An error detection circuit outputs an error detection signal when a number of the output states at the first logical level is other than one, and proceeds to synchronously reset the ring counter when the error condition is detected. A programmable processor further asynchronously resets the ring counter in response to the error detection signal, as desired.