The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2004
Filed:
Aug. 06, 2002
Charvaka Duvvury, Plano, TX (US);
Roger A. Cline, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An output circuit for improved ESD protection (FIG. ) comprising a pMOS pull-up output transistor connected between a signal (I/O) pad and Vdd power supply , the pull-up transistor located in a n-well and having at least one gate , the gate connected to internal circuitry . A dummy pMOS transistor connected in parallel with the pull-up transistor, the dummy transistor also located in the n-well , whereby both the pull-up transistor and the dummy transistor participate in protection against an ESD event. The dummy transistor having at least one gate , this gate connected through a resistor to the Vdd power supply . The n-well connected to the Vdd power supply