The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2004
Filed:
Apr. 24, 2003
Michael Moyal, Munich, DE;
Xignal Technologies AG, Uterhaching, DE;
Abstract
An integrated circuit arrangement comprising a reference-current source device for providing a reference current (Iin) and comprising a current mirror device for mirroring the reference current (Iin) to an output current (Iout), wherein the current mirror device comprises a first FET (Q ), operated in saturation, whose channel carries the reference current; as well as a second FET (Q ), operated in saturation, whose channel carries the output current, wherein the gate connections of the two FETs (Q , Q ) are interconnected in order to ensure identical control voltages (Vgs) at these two FETs (Q , Q ), wherein at a channel connection of the first FET (Q ), a node for generating the reference current (Iin) carried by the channel of this FET is provided from several reference-current components (Iin , Iin ), wherein the reference-current components are provided at the node by the reference-current source device, and one (Iin ) of the reference-current components (Iin , Iin ) is carried by way of a resistance element (Qr) which is connected between the node and the gate connection of the first FET (Q ).