The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2004

Filed:

Jul. 21, 2000
Applicant:
Inventors:

Hsiang-Chou Huang, Pan-Chiao, TW;

Jiin Lai, Taipei, TW;

Nai-Shung Chang, Taipei Hsien, TW;

Assignee:

VIA Technologies, Inc., Taipei Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/100 ;
U.S. Cl.
CPC ...
G06F 1/100 ;
Abstract

An integrated testing method is proposed to perform a test procedure on a number of computer components, concurrently, in a multitasking manner through software simulation. In this method, an initialization procedure is first performed to specify the total number of simulated operations, the FIFO buffer size, the command sequence, and the start time of operation. It is a characteristic feature of this integrated testing method that the test procedure is performed concurrently in a multitasking manner on all the components under test to operate in response to each command from the command sequence. In the event that two or more of the components under test are competing for the same resource, an arbiter is activated to perform arbitration for these competing components.


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Huang, Hsiang-Chou. (2004). Integrated testing method for concurrent testing of a number of computer components through software simulation (U.S. Patent No. 6820219). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6820219

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