Integrated circuit memory devices having efficient column select signal generation during normal and refresh modes of operation and methods of operating same

Abstract

An integrated circuit memory device includes an XY array of memory cell sub-blocks and row and column decoder circuitry that is electrically coupled to the array. The array includes first and second offset grids of sub-word line driver control circuits therein, with each of the sub-word line driver control circuits configured to selectively activate a pair of the memory cell sub-blocks in response to a respective pair of active row and column select signals. In order to improve power consumption requirements when switching back and fourth between normal and refresh modes of operation, the row and column decoder circuitry is configured to drive a selected one of a plurality of row select lines associated with the first grid with an asserted row select signal and a plurality of column select lines associated with the second grid with asserted column select signals during a write operation.