The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 2004

Filed:

Jun. 10, 2003
Applicant:
Inventors:

Takaaki Shirasawa, Tokyo, JP;

Tsuyoshi Takayama, Fukuoka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/704 ;
U.S. Cl.
CPC ...
H03K 1/704 ;
Abstract

In a circuit having MOS transistors connected in series, a surge voltage that occurs during off periods is reduced, while suppressing an increase in switching loss at turning off of the MOS transistors. When a first power MOSFET ( ) is turned off and then a second power MOSFET ( ) is turned on after that according to predetermined timing, the first power MOSFET ( ) is temporarily placed in an on state for a predetermined time period synchronized with that predetermined timing. On the other hand, when the second power MOSFET ( ) is turned off and then the first power MOSFET ( ) is turned on after that according to predetermined timing, the second power MOSFET ( ) is temporarily placed in an on state for a predetermined time period synchronized with that predetermined timing.


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