The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 2004
Filed:
Sep. 27, 2002
Weon-Ho Park, Kyungki-do, KR;
Min-Soo Cho, Kyungki-do, KR;
Jeung-Wook Han, Kyungki-do, KR;
Chil-Hee Chung, Seoul, KR;
Abstract
EEPROM devices may be fabricated by forming a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer on an integrated circuit substrate, and a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and beneath a portion of the gate insulating layer. A first conductive layer, an interlevel insulating layer and a second conductive layer are sequentially formed on the tunnel insulating layer and on the gate insulating layer. The second conductive layer, the interlevel insulating layer and the first conductive layer then are patterned, to define a sense transistor gate on the tunnel insulating layer and on the gate insulating layer that comprises a first portion of the first conductive layer, a first portion of the interlevel insulating layer and a first portion of the second conductive layer, and to further define a select transistor gate on the gate insulating layer and spaced apart from the sense transistor gate, that comprises a second portion of the first conductive layer, a second portion of the interlevel insulating layer, and a second portion of the second conductive layer.