The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2004
Filed:
Mar. 02, 2001
John S. Packer, San Jose, CA (US);
Adaptec, Inc., Milpitas, CA (US);
Abstract
The present invention provides methods for automatically discovering topology map of an I/O subsystem. The I/O subsystem is coupled to one or more host computers and includes one or more peripheral buses, a set of peripheral devices, and a set of expanders with each expander having a valid expander address and being arranged to couple a pair of the peripheral buses. The peripheral devices and the one or more host computers are coupled to the peripheral buses. A host computer selects a peripheral device as a target device and writes a set of entries to the selected target device. Each entry written an expander address field initialized to an invalid expander address for storing an expander address. The host computer then selects the target device and reads the set of entries from the target device. For each expander coupled between the host computer and the target device, the valid expander address associated with the each expander is assigned to one of the expander address fields in the set of entries that contain invalid expander addresses. The host computer receives the set of entries such that the set of the valid expander addresses in the set of entries indicates identity of associated expanders coupled between the host computer and the target device. These operation are repeated for each of the other peripheral devices as the target device so as to discover the topology map of the entire I/O subsystem.