The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2004
Filed:
Mar. 02, 2000
Hiroyuki Ikegami, Tokyo, JP;
NEC Electronics Corporation, Kawasaki, JP;
Abstract
In a logic simulation method, one of an algorithm level simulation and a register transfer level simulation is executed. The algorithm level simulation corresponds to an algorithm level description and the register transfer level simulation corresponds to a register transfer level description. The simulation is switched from one of the algorithm level simulation and the register transfer level simulation into the other in response to a switching instruction using a relation between states of the algorithm level description and states of the register transfer level description. The algorithm level description is associated with arithmetic and logic algorithm and not associated with logic circuits. The register transfer level description is associated with logic circuits.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile