The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 09, 2004

Filed:

Jan. 07, 2003
Applicant:
Inventors:

Kevin E. Atkinson, Eden Prairie, MN (US);

Timothy H. Dwyer, Minneapolis, MN (US);

Ryan C. Johnson, Waconia, MN (US);

Mark D. Elpers, Elk River, MN (US);

Dirk R. Helgemo, Shakopee, MN (US);

Assignee:

MathStar, Inc., Minneapolis, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9177 ;
U.S. Cl.
CPC ...
H03K 1/9177 ;
Abstract

A logic array is provided, which includes a plurality of unidirectional segmented buses connecting a plurality of processing elements, called silicon objects, within an integrated circuit. The bus includes a string of unidirectional bus segments. Each silicon object includes a bus input coupled to one of the bus segments in the first bus, and a bus output coupled to a next subsequent one of the bus segments in the first bus. A landing circuit is coupled to the bus input for receiving digital information from the bus input. A function-specific logic block is coupled to an output of the landing circuit and has a result output. Each silicon object further includes a multiplexer having first and second inputs coupled to the bus input and the result output, respectively, and having an output coupled to the bus output.


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