The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2004
Filed:
Jul. 19, 2002
Applicant:
Inventors:
Bruce L. Trumbo, San Diego, CA (US);
John C. LeVieux, Carlsbad, CA (US);
Assignee:
3Com Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 ;
U.S. Cl.
CPC ...
H03L 7/00 ;
Abstract
In a phase-locked loop, multiple input clock references can each connect to a different interface card. Each interface card can include a phase comparator portion of a phase-locked loop. The phase comparators can produce a phase error signal for a phase-locked loop. One or more of the phase error signals can be transmitted across a bus, such as a time division multiplexed bus, to a system card. The system card can include a controlled oscillator portion of the phase-locked loop. The output of the system card can then sent back to one or more of the interface cards to complete the phase-locked loop.