Phase locked loop

Abstract

A phase locked loop (PLL), which has high operation speed and high resolution, and is particularly applicable in high frequency process, is disclosed. The PLL, receiving a data signal and generating a clock signal, comprises a voltage controlled oscillator (VCO) and multi-phase generator (MPG), a transition detector, an optimal phase encoder, and a phase selector, wherein the four devices are respectively used for outputting N phase clock signals of same frequency but different phases, for outputting a data period value and a clock period value by receiving the N phase clock signals, the data signal and the clock signal, for outputting a phase select signal according to the data period value and the clock period value, and for outputting one of the phase clock signals according to the phase select signal.