The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 02, 2004
Filed:
Apr. 19, 2004
Mark Stadler, Mountain View, CA (US);
Asgeir Thor Eiriksson, Sunnyvale, CA (US);
Kianoosh Naghshineh, Palo Alto, CA (US);
Chelsio Communications, Inc., Sunnyvale, CA (US);
Abstract
A plurality of direct memory access data transfers are accomplished to transfer data from a host to an adaptor. For each transfer, an indication of locations of at least one group of storage locations associated with the host available to hold the data to be transferred to the host is provided from the host to the adaptor. An indication of the provided indication is maintained, for that transfer, by the host. Based on the indication of locations provided from the host to the adaptor, data is transferred to the at least one group of storage locations from the adaptor. An indication is provided from the adaptor to the host that the data transferring step has been completed with respect to the at least one group of storage locations. The host determines the locations corresponding to the at least one group of storage locations based on the indications maintained by the host and retrieving the data from the at least one group of storage locations based on the determination. A similar method is provided to transfer data from the adaptor to the host. Broadly speaking, the host and adaptor retain state information between DMA data transfers. As a result, absolute values of overhead items need not be transferred between the host CPU and the I/O device for each DMA data transfer, and the amount of overhead is reduced.