The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 02, 2004

Filed:

Nov. 16, 2001
Applicant:
Inventor:

Jeffrey L. Deeney, Fort Collins, CO (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/18 ;
U.S. Cl.
CPC ...
H05K 1/18 ;
Abstract

A circuit board assembly has a circuit board and a column grid array (“CGA”) integrated circuit package. The CGA integrated circuit package has a substrate having an array of solder columns extending from a bottom surface. An oversized lid is affixed to the substrate. Support shims are disposed between a portion of the lid that extends beyond an outer periphery of the substrate and a circuit board to which the CGA integrated circuit package is mounted. The support shims are affixed to the lid with adhesive after the CGA integrated circuit package is mounted on the circuit board. The adhesive accommodates any variations in height in the CGA integrated circuit package.


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Deeney, Jeffrey. (2004). Method and apparatus for supporting circuit component having solder column array interconnects using interposed support shims (U.S. Patent No. 6813162). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6813162

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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